1. Field of the Invention
The present invention relates to a phase-change random access memory (“PRAM”) and a method of manufacturing the same, and more particularly, to a PRAM including nanowires and a method of manufacturing the PRAM, the PRAM having improved electrical characteristics by forming metal nanowires in a contact plug formed at a lower portion of a phase change layer.
2. Description of the Related Art
Phase-change materials undergo a structural transformation between crystalline and amorphous phases. The crystalline phase exhibits lower resistance relative to the amorphous phase and has an orderly atomic arrangement. The crystalline phase can be converted to the amorphous phase and vice versa. Phase-change random access memories (“PRAMs”) are devices based on reversible phase change between crystalline and amorphous phases, which have distinctly different resistances.
Generally, PRAMs have a structure in which a contact plug is formed in a source region or a drain region of a transistor, and a phase-change layer and an upper electrode are sequentially formed on top of the contact plugs.
A method of storing data in a PRAM having the general structure described above is as follows. When a current is supplied through an electrode at a lower portion of the phase-change layer, Joule heat is generated in a region where a lower electrode and the phase-change layer contact each other. When the generated Joule heat becomes higher than a re-crystallization temperature, the structure of the phase-change layer is intentionally changed from a crystalline structure to an amorphous phase by appropriately controlling the supplied current. Since a resistance of the phase-change layer varies as it is changed to the amorphous phase, previously stored data values can be distinguished. To change the phase-change layer from the amorphous phase to the crystalline phase, crystallization occurs when a predetermined period of time passes at a temperature lower than a melting point. To change the phase-change layer from the crystalline phase to the amorphous phase, the temperature is increased to approximately the melting point (Tm) of the phase-change layer and then drastically cooled.
Various materials may be used in memory devices. An example of a commonly used material is a material from the chalcogenide family, that is, a GeSbTe (GST) family alloy. In order to improve the quality of PRAM memory devices, current that is supplied should be reduced. In particular, in a case of the most commonly used GST PRAM, a reset current needed to change from the crystalline phase to the amorphous phase is high.
FIGS. 1A and 1B are views of a conventional phase-change memory device disclosed in U.S. Pat. No. 6,800,563.
Referring to FIG. 1A, a lower electrode 11 is formed on top of a substrate (not shown). A phase-change layer 12 and an upper electrode 13 are sequentially formed on top of the lower electrode 11. The width of the lower electrode 11 narrows towards the top of the lower electrode 11 to reduce the area of the lower electrode 11 contacting the phase-change layer 12. That is, by decreasing the area to which current is supplied, more heat is generated.
Referring to FIG. 1B, a lower portion of a GST phase-change layer does not directly contact a lower electrode (BE). Instead, a TiN layer having a narrow width is separately formed so that more heat can be generated from the supplied current.
The structure as illustrated in FIGS. 1A and 1B is for reducing the contact area between the phase-change layer 12 and the area of the lower electrode 11 beneath the phase-change layer 12 to which current is supplied. However, there is a limit to how much the contact area can be reduced due to technical limitations of a semiconductor process. Therefore, a PRAM device with a new structure is required.